The disclosed embodiments are directed to a method for the cross-connection of Synchronous Digital Hierarchy (SDH) signals. The disclosed embodiments are directed to a cross-connection architecture for implementing the method.
The synchronous digital hierarchy (SDH) comprises quite a large entity to be very far advanced in order to transmit time division signals in the telecommunication network. The recommendation CCITT G.707 defines the signals of the first level synchronous transport module (STM-1) for SDH signals having a transmission rate of 155.520 Mbit/s. Other defined levels are STM-4 (633.080 Mbit/s) and STM-16 (2.488.320 Mbit/s). Higher levels are under study. The recommendations CCITT G.708 specify the STM-N (where N=1, 4, 16) frame structure. The basic STM-1 frame is composed of bytes (8 bits), of which there are 2430 including the control blocks; then an STM-1 frame transmits 63 subsystem containers (e.g. TU-1, Tributary Unit, which can contain a 2 Mbit/s signal of a common 30 channel PCM system). The STM-1 frames are repeated 8000 times each second, which is the same as in the subsystem; thus each byte of a frame forms a 64 kbit/s channel. The STM-N frames are combined into logical multiframes. The SDH signals or transport modules are formed by interleaving the bytes of the subsystem signals.
The concept of the digital cross connect was developed in order to ensure a flexible growth of the telecommunications networks and to ensure more developed traffic control modes. Cross connect systems (SDH) DXC (Digital Cross Connect, CCITT draft recommendations G.sdxc-1...-3) are also under development for the synchronous digital hierarchy. The SDH DXC is defined (informally abbreviated): xe2x80x98A digital SDH cross connect is a cross connect device having two or more interfaces at SDH rates (G.707) and being at least able to terminate a transmission section and to controllable, transparently connect and reconnect virtual containers (VC) between the interface portsxe2x80x99.
An SDH DXC can transmit traffic between different SDH levels and connect traffic between different signals. The use of the cross connect also includes a possibility for remote control of routing, initialization of reserve routes, connection from one signal to several signals (broadcasting), and so on. The connections are usually bothway connections.
The mentioned CCITT SDH recommendations try to define the logical function, i.e. a functional structure of devices, but they avoid the detailed structural description of the devices.
The digital cross connect has already been studied a long time in order to find an architecture which meets the optimal conditions. A structure which readily meets the conditions regarding capacity, non-blocking properties and implementation, is the TST (Time-Space-Time) structure, or the time-space-time cross connect, schematically shown in FIG. 1. On the left in the figure there are the input signals I1 . . . In (here STM-1 signals) and on the right there are the output signals O1...On. The time switches Ti1 . . . Tin and To1 . . . Ton on the input side and output side, respectively, change the byte positions (within a frame) within a signal. The central space switch S transmits a signal from one time switch to a signal directed to another time switch. In principle the time switches are memory elements and the space switch is composed of switch elements. According to prior art the cross connect is implemented as a module structure. The TST cross connect is also suited for very large cross connects, although then some problems arise when the system grows.
Usually the STM-1 signals are logically cross-connected on the basis of bytes through the TST switch. The byte based switching means that the actual connection is performed at the SDH TU-12 level, i.e. logically 2 Mbit/s streams are connected. The logical connection rate per STM-1 signal is about 155 Mbit/s both in the time switches and in the space switch.
The problem is primarily created by the space switch. When the capacity of the space switch is exceeded the expansion is quadratic. When for example the 16xc3x9716 basic module (16xc3x9716 STM-1) of the space switch according to FIG. 2 becomes full, then the next step is 32xc3x9732, which is realized by four 16xc3x9716 basic modules. Problems caused by the quadratic expansion are i.a.:
a) the connectors: the addition of modules always leads to multiple signal interfaces, as is shown in the example of FIG. 3. The number of connector pins increases, and sufficient physical connectors cannot be found anymore when we arrive at large space switches. Problems are not caused only by the number of pins, but also by cables, the physical strength of the printed boards, and so on;
b) thermal power: the expansion also causes multiple input/output driver circuits in the cross connect, whereby the power consumption within a module increases too much;
c) space/distance: the quadratic expansion in large cross connects causes problems regarding the available space and the data transmission rates and synchronization of the signals when the distances between the basic modules of the space switch increase considerably.
Further it must be observed that even a preparation for the expansion causes the disadvantages according to points a) and b) above, in other words, when we make preparations for a very large expansion, then the interfaces required by the expansion reduce the maximum capacity of the basic module, or the planned maximum capacity as such accelerates the quadratic expansion. FIG. 3 illustrates the quadratic expansion in a situation where the space switch has to switch a quadruple number, or 64 input signals to 64 output signals. Then the required number of basic modules increases to 16.
The object of the invention is now to present for the cross-connection of SDH signals a method and an architecture realizing the method, with which the need for the quadratic expansion can be postponed to a much later point. The object is also to reduce the number of required space switch modules in large cross connects.
Thus in a conventional TST cross connect structure xe2x80x98packetsxe2x80x99 or bytes comprising 8 consecutive bits are connected through the cross connect. For this byte or these 8 bits the space switch thus makes only one new connection at the beginning of the byte, and the rest of the time the bits are connected through the switch by the same routing (this is what happens logically thinking; in practice the bits of the byte may be rearranged and connected in some suitable form within the space switch). It could be said that in the conventional solution each byte xe2x80x98consumesxe2x80x99 the interface capacity of the space module, in other words the maximum number of signals in the module depends on the transmission capacity (the bit rate) and the number of pins in the connectors.
The implementation of the invention is based on the fact that the time slot of a byte is utilized more efficiently, or the logical unit (=byte) is divided into smaller parts, and the parts or the bits of the byte are transmitted in parallel form through the space switch. Then the capacity of the space switch is utilized more efficiently. The implementation is also based on the fact that then each bit can be switched through the space switch independently of the other bits in the byte.
Parallell bit processing as such is no novelty. For example digital central offices have used time-space-time switches, in which the bytes are switched in a parallel mode through the switch means. This however relates to the fully parallel processing of the bits in a 2 Mbit/s channel time slot, both through the time and the space switch, whereby all bits in the time slot (byte) are processed in parallel, and the byte is connected in parallel mode through the whole TST switch. The primary goal has been to reduce the operating rate of the switches, but the logical structure of processing of the byte was not concerned. (See e.g. J-H. Pasanen, R. Mxc3xa4ihxc3xa4niemi: xe2x80x98Vxc3xa4litystekniikan perusteetxe2x80x99 (Switching Technology Basics), p. 180-191; The Students"" Union at the University of Technology, Otaniemi, Finland, 1975.) In the present invention the bytes are instead treated in a different way in the time switches and in the space switch, and further the bits of the byte can be processed in the space switch independently of the other bits. The present invention further relates to the cross-connection of SDH signals.
According to the invention, in the time switch at the input side of the cross connect, each byte is divided into parts or into bits, which are disassembled into a xe2x80x98parallel formxe2x80x99, or the parts are transmitted to separate lines. The lines of these partial bytes are connected to the space switches. When the division is made into bits, 8 space switches are now required for each basic module. On the other hand the capacity or the number of input lines and output lines of the module increases in the same proportion, or it will be eightfold. As an example the 16xc3x9716 space switch of FIG. 1 will now be a 128xc3x97128 switch, which earlier required 64 space switch modules (or 8xc3x978). With the aid of this we can use linear expansion to the eightfold capacity, compared to the earlier situation.
As an alternative for the division of the byte into bits it is conceivable to divide the byte after the time switch into two half-bytes, which then are switched through different space switches to the time switch on the output side. Then 32 space modules would be required for a 128xc3x97128 space switch.
Another implementation in the invention is to combine the bits of several STM-1 signals of the same value for the transmission between the switches into xe2x80x98packetsxe2x80x99, for example so that always the same value bits from four STM-1 signals are taken and multiplexed into a serial mode xe2x80x98packetxe2x80x99 before the transmission to the space switch. Then the multiplexing is made in the transmitting time switch elements, and after the transmission a corresponding demultiplexing is made in the space switch. A corresponding operation is repeated between the space switch and the output time switches. The multiplexing is here a physical operation for the transmission, whereby one conductor pair for each transmitted xe2x80x98packetxe2x80x99 will be enough between the switch modules, or if four bits are combined, then also the corresponding number of connector pins and driver circuits of the connectors will decrease to a fourth. The multiplexing/demultiplexing slightly increases the need for circuits, but in an advantageous way this could be handled by circuit integration solutions. The savings in connector pins and driver circuits (space; power) is a much more important achievement.
The method and the cross-connection architecture can be used at all SDH levels, or for the cross-connection of all defined signals STM-1. . . STM-16 and of other corresponding signals. While the enclosed figures are based on a traditional space switch module, which has 16 input and 16 output interfaces for STM-1 signals, it is quite natural that smaller and particularly bigger signal line numbers can be applied within the inventive idea, so that e.g. in bit based space switching it is possible to use space switch modules having more than 128xc3x97128 signal interface lines.
According to the present invention the capacity of the space switch modules in the cross connect will be efficiently used, and accordingly the number of the used modules will decrease considerably when we go towards larger cross connects. Now it is possible to delay the quadratic expansion to a much later point.
The invention is described below with the aid of examples with reference to the enclosed figures.